This invention relates to semiconductor devices having one or more resistor elements produced with one or more polycrystal semiconductor layers and to methods for production thereof.
Static random access memory devices having 6-element cells can be classified into a group which utilizes one or more depletion transistors as one or more resistor elements and another group which has one or more resistor elements produced with one or more high resistance polycrystal semiconductor layers. Albeit the former is easy to produce, it involves the disadvantage of a lesser integration. Therefore, it is observed that the latter group is more frequently employed.
Static random access memory devices which have one or more resistor elements produced with one or more high resistance polycrystal semiconductor layers are further classified into two groups. One has a single layer and the other has plural layers. The latter is of course advantageous from the viewpoint of integration.
A prior invention by the same inventor was devices in which power supply (V.sub.DD) lines and registor elements are produced from the first or lower polycrystal semiconductor layer, and wirings for various purposes including those for connection of transistors are produced with the upper polycrystal semiconductor layers. This prior art subject matter is for instance discussed in prior U.S. Pat. 4,326,213 issued Apr. 20, 1982.
Description of the subject matter of this prior art is now summarized below, referring to FIGS. 1 through 4, which respectively show a wiring diagram of a static random access memory cell, a schematic plan view of a major portion of a static random access memory device, a cross-sectional view of this plan view taken along the line A--A' and a cross-sectional view along the line B--B'.
The memory cell 10 includes transistors Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4, load resistor R.sub.1 and R.sub.2, a power supply line V.sub.DD, the bit lines 11, 12, a word line 13, a field numerals (20) 20, (21) respectively depict a field oxide layer 21 and a portion of a first or lower polycrystal semiconductor layer which constitutes the power supply line V.sub.DD, various portions 21a to 21d of the first or lower polycrystal semiconductor layer which respectively constitute different wirings, windows or openings 22, 23, portions 24, 25 of a second polycrystal semiconductor layer which constitute independent wirings, a source region 26 provided commonly for both the transistors Q.sub.1 and Q.sub.2, a window or an opening 27 for contacting an electrode, a drain region 28 and the edge 29 of the drain region, a window, or an opening 30, a silicon gate 31 of the transistor Q.sub.1, a silicon gate 32 of the transistor Q.sub.2, a drain region 33 provided commonly for both the transistors Q.sub.2 and Q.sub.4, a source region 34 of the transistor Q.sub.4, a contact window 35, a source region 36 of the transistor Q.sub.3, a contact window 37, a drain region 38 of the transistor Q.sub.3, a phosphosilicate glass film 39 and an oxide film 40.
In the above described arrangement, a plurality of polycrystal semiconductor layers is employed. In this sense, the degree of integration is improved to a considerable extent. It is noted, however, that the plural layer configuration is not applied to the high resistance polycrystal conductive layers. In other words, the plural layer configuration is not applied to the memory cell region and the application of the plural layer configuration for the polycrystal semiconductor layers is limited to the field region. In this sense, the present invention provides further improvement.